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  1. Graduate College
  2. ECE – Electrical and Computer Engineering - Graduate Catalog
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  4. Fault modelling and simulation for the test of integrated analog and mixed-signal circuits

Abstract Keywords 9 Abstract Although most electronic circuits are almost entirely digital, many include at least a small part that is essentially analog. Author supplied keywords Analog and mixed-signal test Built-in self-test Defect-oriented test Design-for-test Design-for-testability Fault modelling Fault simulation Self-checking circuits Test generation.

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Test and Design-for-Testability in Mixed-Signal Integrated Circuits deals with test and design for test of analog and mixed-signal integrated circuits. Especially in System-on-Chip SoC , where different technologies are intertwined analog, digital, sensors, RF ; test is becoming a true bottleneck of present and future IC projects. Linking design and test in these heterogeneous systems will have a tremendous impact in terms of test time, cost and proficiency.

Although it is recognized as a key issue for developing complex ICs, there is still a lack of structured references presenting the major topics in this area. The aim of this book is to present basic concepts and new ideas in a manner understandable for both professionals and students.

Since this is an active research field, a comprehensive state-of-the-art overview is very valuable, introducing the main problems as well as the ways of solution that seem promising, emphasizing their basis, strengths and weaknesses.

Graduate College

In essence, several topics are presented in detail. Standardization is another topic considered in the book, with focus on the IEEE Another digital testing scheme, which uses a divide and conquer approach, is found in E. McCluskey and S.

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C, No. Analog circuits also need to be designed for testability. The typical analog circuit is more difficult to test than the typical digital circuit, for reasons including the following.

ECE – Electrical and Computer Engineering - Graduate Catalog

Analog modules are tightly coupled, with everything depending on everything else. Design margins are tight for analog circuits, as compared with large safety margins built into digital circuits. There is no ability to freeze internal states, such as charge on capacitors, of analog circuits, while the digital circuits have enable signals or clocks. Analog circuits are sensitive to input noise and output loading effects. There is no formal specification for analog functions, unlike the simple boolean equations or hardware description languages used in the digital world.

These include.

Wagner and T. Fasang et al. Soma etc.

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Continuity of normal signal path between submodules whether at chip or board level is not ensured. This implies that after the completion of individual testing for submodules, additional testing at the next higher level is still necessary to ensure the proper connection between submodules. Applicability of each scheme is often restricted to a specific topology or a specific class of analog circuits.

For example, a popular misrepresentation of analog circuits consists of a linear chain of analog blocks, each having exactly one input and one output. This misrepresentation leads to testing schemes which lack general applicability. Isolate the analog portion from a mostly-digital circuit, such that analog testing can be dealt with later by someone else. This approach does not work for mostly-analog circuits, or cases when the analog testing is too complex;.

Only DC static testing for the analog block can be done in this case, while real time AC dynamic testing is not feasible. The object of the invention is achieved by placing three-way analog switches at selected ports of circuit modules. The invention will now be described by way of non-limitative example with reference to the following drawings.

Fault modelling and simulation for the test of integrated analog and mixed-signal circuits

For the purposes of this document, the following definitions will be used. The phrase IC package is used interchangeably with the word "chip". The word carrier means any medium carrying circuit modules testable using the invention. Printed circuit boards are an example of a carrier. The word "port" means any electrical signal connection to a module, such as a pin on a chip or a connector on a printed circuit board.

The three-way switch is composed of two transmission gates T 1 and T 2 and is disposed between two submodules A and B. Under control of D flip-flops , The three-way switch allows transmission along one of three paths: i a normal data path form A to B, ii a first test path from the test bus to B, or iii a second test path from A to the test bus. The switch can assume the states of the following table.

Introduction to Design for testability (Digital VLSI course)

The flip-flops in turn are controlled by input data signals on the port Data in, and by their clock and reset inputs. As explained in the prior patent, the three-way switch can also contain three transmission gates as well as two. Boxes and are the same as in FIG. There are two output ports, OUT and D -- out, corresponding to the output from block to submodule B and Data out, respectively. There is a bi-directional test port corresponding to the connection from block to the test bus. The IC package contains a core circuit which performs the principal function of the IC. The core circuit has internal inputs and outputs which are connected to the ports of the package via switching cells according to FIG.

In this case, six such internal inputs and outputs are shown The test ports of cells , , and are connected to a test bus wire ATBO.